Documentation

How to: many-accelerator SoC


What you learn

  • Generate a many-accelerator SoC with the ESP GUI

  • Test the SoC

    • Run full-system RTL simulation

    • Test on FPGA both bare-metal and with Linux

<add a figure showing a flow chart of the 4 steps described in what you learn>


What you need


What you do

Tutorial guide:

Guide

Tutorial video:


What you can read

Handling Large Data Sets for High-Performance Embedded Applications in Heterogeneous Systems-on-Chip
Paolo Mantovani, Emilio G. Cota, Christian Pilato, Giuseppe Di Guglielmo, and Luca P. Carloni
In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2016

PAPER


What you could contribute

Future work:

  • Design partitioning across multiple FPGA to prototype larger SoCs

  • Partial bitstream support to speedup the bitstream generation and to enable runtime reconfiguration of tiles