This release moves main-memory access from AHB to AXI, improves AXI-to-NoC burst transfers, makes the FPGA memory-link width configurable, and enables two memory tiles on VCU118. It also refreshes the SoC configuration GUI, updates the Catapult SystemC flow and ASIC build infrastructure, expands AXI support across the supported FPGA boards, and includes a collection of architecture, software, and build fixes.

See the official release notes for the full list of changes.

Check out the release notes for the complete list of new ESP features.

The chip features multiple Linux-capable RISC-V cores, 14 different types of accelerators, and novel power management techniques.

This work is a collaboration with Harvard, IBM Research, and University of Illinois and was recently published at ISSCC 2024.

Check out the release notes for the complete list of new ESP features.

Check out the release notes for the complete list of new ESP features.

This work is a collaboration with Harvard and IBM Research and was recently published at ESSCIRC 2022.

Check out the release notes for the complete list of new ESP features.

Co-located at ISCA 2022, OSCAR aims at fostering the community of researchers who are interested in developing and sharing open-source hardware and software for the design of next-generation computer architectures. For more details and logistics, check out the workshop website available here.

Abstract:

One of the most critical aspects of integrating loosely-coupled accelerators in heterogeneous SoC architectures is orchestrating their interactions with the memory hierarchy, especially in terms of navigating the various cache-coherence options: from accelerators accessing off-chip memory directly, bypassing the cache hierarchy, to accelerators having their own private cache. By running realsize applications on FPGA-based prototypes of many-accelerator multi-core SoCs, we show that the best cache-coherence mode for a given accelerator varies at runtime, depending on the accelerator’s characteristics, the workload size, and the overall SoC status.

Cohmeleon applies reinforcement learning to select the best coherence mode for each accelerator dynamically at runtime, as opposed to statically at design time. It makes these selections adaptively, by continuously observing the system and measuring its performance. Cohmeleon is accelerator-agnostic, architectureindependent, and it requires minimal hardware support. Cohmeleon is also transparent to application programmers and has a negligible software overhead. FPGA-based experiments show that our runtime approach offers, on average, a 38% speedup with a 66% reduction of off-chip memory accesses compared to state-of-the-art design-time approaches. Moreover, it can match runtime solutions that are manually tuned for the target architecture.

Abstract: The open-source hardware community contributes a variety of processors and accelerators, but combining them effectively into a complete System-on-Chip (SoC) remains a difficult task. We present a design flow for the seamless hardware and software integration of accelerators into a complete SoC and for its evaluation through rapid FPGA-based prototyping. By leveraging ESP, our open-source platform for agile heterogeneous SoC design, we demonstrate FPGA prototypes of various SoC designs, featuring the NVIDIA Deep Learning Accelerator and the Ariane RISC-V 64-bit processor core.