The open-source heterogeneous
system-on-chip platform


ESP is an open-source research platform for heterogeneous system-on-chip design. The platform combines an architecture and a methodology. The flexible tile-based architecture simplifies the integration of heterogeneous components by balancing regularity and specialization. The companion methodology raises the level of abstraction to system-level design, thus promoting closer collaboration among software programmers and hardware engineers.

  • Architecture
    • Tile-based architecture: processor, memory and accelerator tiles
    • NoC-based
    • Available processors
  • CAD
    • Seamless accelerator design flows: RTL (Chisel) and HLS (C, SystemC) systemc-logo.png chisel-logo.jpg
    • Mix & match floorplanning GUI
    • Rapid FPGA prototyping
  • Hardware linux-logo.png
    • Linux SMP support
    • Supported FPGA boards
      • Xilinx Virtex UltraScale+ FPGA VCU118
      • Xilinx Virtex-7 FPGA VC707
      • proFPGA quad V7 Prototyping System, hosting 4 Xilinx Virtex7 FPGAs profpga-logo.jpg

What’s new

  • ESP open-source release

Coming soon

  • Integration of the NVIDIA Deep Learning Accelerator (NVDLA)

  • Support for Vivado HLS accelerators

  • Support for third-party accelerators with AXI interface

  • Multi-processor support for the RISC-V Ariane cores

  • Support for Digilent Genesys2 FPGA board

Latest Posts

Upcoming tutorial at the ESWeek in New York
Upcoming tutorial at the ESWeek in New York

Join us in New York on October 13th at the Embedded Systems Week for the first ever ESP tutorial!

ESP Release
ESP Release

The ESP open-source platform has been released!