Overview Paper on ESP
Agile SoC Development with Open ESP
Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
(Invited) IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020
Publications on ESP
Accelerator Integration for Open-Source SoC Design
Davide Giri, Kuan-lin Chiu, Guy Eichler, Paolo Mantovani, Luca P. Carloni
IEEE Micro (Special Issue: FPGAs in Computing), 2021
Scalable Open-Source System-on-Chip Design
Luca P. Carloni
(Invited Talk - Extended Abstract) IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2020
Design and Integration of a Debug Unit for Heterogeneous System-on-Chip Architectures
Gabriele Tombesi, Advisors: Luciano Lavagno, Luca P. Carloni
Master’s Thesis, Politecnico di Torino, 2020
Ariane + NVDLA: Seamless Third-Party IP Integration with ESP
Davide Giri, Kuan-lin Chiu, Guy Eichler, Paolo Mantovani, Nandhini Chandramoorthy, Luca P. Carloni
Workshop on Computer Architecture Research with RISC-V (CARRV), 2020
ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning
Davide Giri, Kuan-lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni
(Best Paper Nominee) Design, Automation and Test in Europe Conference (DATE), 2020
Runtime Reconfigurable Memory Hierarchy in Embedded Scalable Platforms
Davide Giri, Paolo Mantovani, Luca P. Carloni
(Invited) Asia and South Pacific Design Automation Conference (ASPDAC), 2019
Accelerators and Coherence: An SoC Perspective
Davide Giri, Paolo Mantovani, Luca P. Carloni
IEEE Micro (Special Issue: Hardware Acceleration), 2018
NoC-Based Support of Heterogeneous Cache-Coherence Models for
Accelerators
Davide Giri, Paolo Mantovani, Luca P. Carloni
IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018
Scalable System-on-Chip Design
Paolo Mantovani, Advisor: Luca P. Carloni
PhD Thesis, Columbia University, 2017
Broadening the Exploration of the Accelerator Design Space in Embedded
Scalable Platforms
Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
IEEE High Performance Extreme Computing Conference (HPEC), 2017
Handling Large Data Sets for High-Performance Embedded Applications in
Heterogeneous Systems-on-Chip
Paolo Mantovani, Emilio G. Cota, Christian Pilato, Giuseppe Di Guglielmo, Luca P. Carloni
International Conference on Compilers, Architecture and Synthesis
for Embedded Systems (CASES), 2016
The Case for Embedded Scalable Platforms
Luca P. Carloni
(Invited) Design Automation Conference (DAC), 2016
An FPGA-based Infrastructure for Fine-grained DVFS Analysis in High-performance
Embedded Systems
Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato, Giuseppe
Di Guglielmo, Ken Shepard, Luca P. Carloni
Design Automation Conference (DAC), 2016
High-Level Synthesis of Accelerators in Embedded Scalable
Platforms
Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni
(Invited) Asia and South Pacific Design Automation Conference (ASPDAC), 2016
Papers using ESP
MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems
Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragon, Luca P. Carloni, Margaret Martonosi
(Best Paper Nominee) IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), 2020
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely
Coupled Accelerators
Luca Piccolboni, Giuseppe Di Guglielmo, Luca P. Carloni
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2018
System-Level Design of Networks-on-Chip for Heterogeneous
Systems-on-Chip
Young Jin Yoon, Paolo Mantovani, Luca P. Carloni
(Invited) IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2017
Other relevant papers
Teaching Heterogeneous Computing with System-Level Design Methods
Luca P. Carloni, Emilio G. Cota, Giuseppe Di Guglielmo, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca Piccolboni, Michele Petracca
Workshop on Computer Architecture Education (WCAE), 2019
From Latency-Insensitive Design to Communication-Based System-Level Design
Luca P. Carloni
The Proceedings of the IEEE, Vol. 103, No. 11, November 2015