Published: Nov 26, 2019 by Davide Giri
Join Luca in San Jose on December 11th for a talk about ESP at the RISC-V Summit: Prototyping RISC-V Based Heterogeneous Systems-on-Chip with the ESP Open-Source Platform.
ESP allows rapid FPGA prototyping of complex SoCs based on RISC-V processors. By combining a modular tile-based architecture with a flexible design methodology, ESP simplifies the development and integration of coarse-grain accelerators as well as the reuse of third-party open-source components. With ESP’s automation capabilities, we can rapidly prototype, for example, an SoC that features: the Ariane RISC-V processor core booting Linux, a multi-plane network-on-chip supporting a partitioned memory hierarchy with multiple DRAM controllers, and tens of accelerators, including the NVIDIA NVDLA as well as accelerators designed with various languages and synthesis tools (C with Vivado HLS, SystemC with Stratus HLS, Keras TensorFlow and PyTorch with hls4ml, Chisel, and Verilog/VHDL). Compared to other RISC-V related projects, ESP is focused on scalability (with a NoC-based architecture), heterogeneity (with emphasis on loosely-coupled accelerators), and flexibility (with support of different design flows).