Our paper “ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded
Machine Learning” has been accepted at DATE 2020.
We will present the tutorial
“ESP: An Open-Source Platform for Interdisciplinary Research on SoC Design and
Programming” at ASPLOS 2020 on March 17th in
We will give a talk about ESP in Bangalore (India) on January 5th at the
International Conference on VLSI Design and International Conference on Embedded
Design (VLSID & ES).
Join Luca in San Jose on December 11th for a talk about ESP at the
Prototyping RISC-V Based Heterogeneous Systems-on-Chip with the ESP Open-Source Platform.
It is now possible to create an ESP instance with one or multiple accelerator
tiles hosting the NVIDIA Deep Learning Accelerator (NVDLA).
This feature is available with RISC-V only, when selecting
Ariane for the ESP processor tile.