Integrate ASIC Memory Macros

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What you will learn

• Integrate ASIC memory macros from any technology into ESP
  • project setup and directory structure
  • ESP memory requirements
  • automatic generation of memory wrapper skeletons
  • editing memory wrappers for the ESP memory protocol and the memory macro interface
  • running HLS for ESP-integrated accelerators
  • configuring an SoC with shared local memory (SLM) and accelerator tiles
  • automatic generation of SLM memory banks
  • SoC, accelerator and SLM RTL simulation

What you will need

• Prerequisites
  • Set up ESP
  • Design a single-core SoC
• Technology files
  • Memory models (Verilog, Liberty and LEF)
  • Standard cell models (Verilog, Liberty and LEF)

What you can read

What you can contribute

The ESP team welcomes external contributions and collaborations, including:

• Accelerator designs for a wide range of application domains
• Support for more HLS tools
• Accelerator design flows from domain-specific languages (DSLs)
• A power estimation flow

See the contributing guidelines.