How to: integrate ASIC memory macros into ESP
Tutorial guide:
What you will learn
- Integrate ASIC memory macros from any technology into ESP
- Project setup and directory structure
- ESP memory requirements
- Automatic generation of memory wrapper skeletons
- Edit memory wrappers according to ESP memory protocol and memory macros interface
- Execute HLS for ESP integrated accelerators
- Configure a SoC with Shared Local Memory (SLM) and accelerator tiles
- Automatically generate SLM memory banks
- SoC, accelerator and SLM RTL simulation
What you will need
- Prerequisites
- Equipment
- Memory models from any technology (Verilog, Liberty and LEF)
- Standard cells models from any technology (Verilog, Liberty and LEF)
- (optional) An internet router
What you can read
Agile SoC Development with Open ESP
Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni
(Invited) IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2020
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components
Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth Shepard, Luca P. Carloni, and Pradip Bose
(Invited) IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022
What you can contribute
The ESP team welcomes external contributions and collaborations on a variety of topics including but not limited to:
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Accelerator designs for a wide range of application domains
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Support for more HLS tools
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Support for accelerator design flows from domain-specific languages (DSL).
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Power estimation flow
Check out our contributing guidelines.