Design a Single-Core SoC

Open the guide

Tutorial video:

Note: The video tutorial was not recorded with the latest version of the ESP repository. While watching the video, please refer to the written tutorial guide for the most up to date instructions.

What you will learn

• Generate a minimal ESP SoC with the ESP GUI
• Use the AMD/Xilinx build and programming flow, or preview the upcoming Intel/Altera flow
• Test the SoC
  • Run full-system RTL simulation
  • Test on FPGA both in bare-metal and with Linux
  • Connect to the SoC with SSH

What you will need

• Prerequisites
  • How to: setup
• Equipment
  • One of the supported FPGA boards (see homepage)
  • (optional) An internet router
• (optional) Prebuilt material
  • Current prebuilt material targets AMD/Xilinx boards
  • The FPGA bitstream (top.bit) generated in the tutorial
  • The Linux image (linux.bin) generated in the tutorial
  • The bare-metal binaries (systest.bin, prom.bin) generated in the tutorial

What you can read

The Case for Embedded Scalable Platforms
Luca P. Carloni
(Invited) In Proceedings of the Design Automation Conference (DAC), 2016

PAPER

What you can contribute

The ESP team welcomes external contributions and collaborations on a variety of topics including but not limited to:

• Support for more FPGA targets

• Power estimation flow

• ASIC backend flow

Check out our contributing guidelines.