How to: integrate an ASIC technology into ESP

Tutorial guide:


What you will learn

  • Project setup and directory structure
  • Integrate ASIC memory macros into ESP
    • ESP memory requirements
    • Automatic generation of memory wrapper skeletons
    • Edit memory wrappers according to ESP memory protocol and memory macro interfaces
    • Test memory wrappers with generated testbenches
  • Integrate ASIC IO cells into ESP
    • Automatic generation of IO wrapper skeletons
    • Edit pad wrappers according to ESP IO protocol and pad macro interfaces
  • Execute HLS for ESP integrated accelerators
  • Configure an SoC with Shared Local Memory (SLM) and accelerator tiles
    • Automatically generate SLM memory banks
  • RTL simulation using ASIC technology

What you will need

  • Prerequisites
  • Equipment
    • Memory models from any technology (Verilog, Liberty and LEF)
    • IO cell models from any technology (Verilog, Liberty and LEF)
    • Standard cell models from any technology (Verilog, Liberty and LEF)

What you can read

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components
Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth Shepard, Luca P. Carloni, and Pradip Bose
(Invited) IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022


14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration
Maico Cassel Dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla Rodriguez, John-David Wellman, En-yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita Adve, Pradip Bose, David Brooks, Luca Carloni, Kenneth Shepard, and Gu-Yeon Wei. Proceedings of the IEEE International Conference on Solid-State Circuits (ISSCC), 2024.


What you can contribute

The ESP team welcomes external contributions and collaborations on a variety of topics including but not limited to:

  • Accelerator designs for a wide range of application domains

  • Power estimation flow

  • ASIC design scripts with open-source tools

Check out our contributing guidelines.