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Integrate an ASIC Technology

Bring memory macros, I/O cells and standard cells into ESP

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What you will learn

  • Project setup and directory structure
  • Integrate ASIC memory macros into ESP
    • ESP memory requirements
    • automatic generation of memory wrapper skeletons
    • editing memory wrappers for the ESP memory protocol and the memory macro interfaces
    • testing memory wrappers with generated testbenches
  • Integrate ASIC I/O cells into ESP
    • automatic generation of I/O wrapper skeletons
    • editing pad wrappers for the ESP I/O protocol and the pad macro interfaces
  • Run HLS for ESP-integrated accelerators
  • Configure an SoC with shared local memory (SLM) and accelerator tiles
    • automatic generation of SLM memory banks
  • Run RTL simulation with the ASIC technology

What you will need

  • Prerequisites
  • Technology files
    • Memory models (Verilog, Liberty and LEF)
    • I/O cell models (Verilog, Liberty and LEF)
    • Standard cell models (Verilog, Liberty and LEF)

What you can read

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components

Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth Shepard, Luca P. Carloni, and Pradip Bose

Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), 2022

Paper Slides Video

A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management, and Flexible NoC-Based Data Orchestration

Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, En-Yu Yang, John-David Wellman, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita Adve, Pradip Bose, David Brooks, Luca Carloni, Kenneth Shepard, Gu-Yeon Wei

Proceedings of the International Solid-State Circuits Conference (ISSCC), 2024

Paper

What you can contribute

The ESP team welcomes external contributions and collaborations, including:

  • Accelerator designs for a wide range of application domains
  • A power estimation flow
  • ASIC design scripts with open-source tools

See the contributing guidelines.