Skip to content

C/C++ Accelerator with AMD/Xilinx Vivado HLS

Design, synthesize and integrate a C/C++ accelerator

Open the guide

Platform support: ESP's HLS flows currently target AMD/Xilinx FPGA technology mappings and are not supported by the Intel/Altera DE10-Pro SX flow. Use an RTL or Third-Party accelerator on that board.

For a video walkthrough of the common accelerator flow, see the SystemC accelerator tutorial.

What you will learn

  • Generate a customized accelerator
    • source code skeleton
    • testbench
    • Vivado HLS synthesis scripts
    • device driver
    • user-space application skeleton
  • Implement accelerator-specific code in C++
    • computation kernel
    • input and golden output
    • validation
  • Integrate a new accelerator into an ESP instance and test it on FPGA

C/C++ accelerator design workflow

What you will need

  • Prerequisites
  • Equipment
    • A supported AMD/Xilinx FPGA board (see FPGA targets)
    • (optional) A network router, to reach the SoC over SSH
  • (optional) Prebuilt material
    • The source code, testbench and Vivado HLS scripts for the MAC accelerator
    • The device drivers for the MAC accelerator
    • Working folders for the AMD/Xilinx VCU118 and VC707

What you can read

ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning

Davide Giri, Kuan-lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni

(Best Paper Nominee) Design, Automation and Test in Europe Conference (DATE), 2020

Paper Slides Video Tutorial

What you can contribute

The ESP team welcomes external contributions and collaborations, including:

  • Accelerator designs for a wide range of application domains
  • Support for more HLS tools

See the contributing guidelines.