How to: design a partially-reconfigurable SoC


Tutorial video:

What you will learn

  • The FPGA flow to generate a partially-reconfigurable SoCs in ESP
  • The FPGA flow for incremental compilation of accelerators
  • Test the SoC
    • Test runtime reconfiguration (swapping) of accelerators on FPGA both in baremetal and with Linux

What you will need

What you can read

An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs
Biruk Seyoum


What you can contribute

The ESP team welcomes external contributions and collaborations on a variety of topics including but not limited to:

  • Support for a nested (fine-grained) reconfiguration flow
  • Support for an improved partial-reconfiguration software runtime manager

Check out our contributing guidelines.