Legacy documentation: the DPR targets, runtime API and
example described here are not present in the current ESP source tree. This
page is kept as a historical reference for the earlier AMD/Xilinx flow; do not
treat its commands as instructions for the current release. The most recent
public DPR development work is on the
esp_dpr_flow_integration
branch, which is not part of an ESP release.
Legacy
What you will learn
- The historical FPGA flow used to generate partially reconfigurable SoCs in ESP
- The FPGA flow for incremental compilation of accelerators
- Test the SoC
- Test run-time reconfiguration (swapping) of accelerators on FPGA with both bare-metal applications and Linux
What you will need
- Prerequisites
- Equipment
- The historical guide targets the AMD/Xilinx VC707. Later VCU118 and VCU128 work is version-sensitive and lives on the DPR development branch linked above.
What you can read
PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCs
Design, Automation and Test in Europe Conference (DATE), 2023
An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs, Biruk Seyoum.
What you can contribute
The ESP team welcomes external contributions and collaborations, including:
- A nested (fine-grained) reconfiguration flow
- An improved partial-reconfiguration software runtime manager
See the contributing guidelines.