The Third-Party flow integrates an accelerator with a 64-bit AXI4 memory master, 32-bit APB configuration slave and interrupt. It is supported by both the AMD/Xilinx flow and the unreleased Intel/Altera development flow.
Intel/Altera support and the Vortex integration are not part of a released
ESP version yet. Coming soon
What you will learn
- How the current AXI-to-NoC socket handles bursts, transfer sizes, write strobes and coherent or non-coherent memory traffic
- How to describe, wrap, compile and register a new third-party accelerator
- How to configure and prototype an SoC with third-party accelerator tiles
- How ESP integrates NVDLA and the programmable Vortex RISC-V GPGPU Coming soon
Prerequisites
- Set up ESP
- Design a single-core SoC
- Access to a supported FPGA board for the prototyping sections
Related reading
- Accelerator Integration for Open-Source SoC Design, IEEE Micro, 2021
- Ariane + NVDLA: Seamless Third-Party IP Integration with ESP, CARRV 2020
- ESP contribution guidelines
Useful contribution areas include new accelerator integrations, additional bus adapters, Vortex runtime and workload support, and NVDLA runtime or network support.