Platform support: ESP's HLS flows currently target AMD/Xilinx
FPGA technology mappings and are not supported by the Intel/Altera DE10-Pro SX
flow. Use an RTL or
Third-Party accelerator on that board.
What you will learn
- Implement an accelerator for Catapult HLS in SystemC
- two accelerator coding styles for different MatchLib memory-modeling options, plus one coding style for a bottom-up design flow
- the extended
load,compute_dataReq,compute,store_dataReqandstorestructure of an accelerator - testbench
- Catapult HLS synthesis scripts
- device driver
- user-space application
- validation
- Integrate a new accelerator into an ESP instance and test it on FPGA
- Synthesize a multi-module accelerator bottom-up and, on the development branch, map its memories to UltraScale+ URAM Coming soon
What you will need
- Prerequisites
- Equipment
- A supported AMD/Xilinx FPGA board (see FPGA targets)
- (optional) A network router, to reach the SoC over SSH
What you can read
Agile SoC Development with Open ESP
(Invited) IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2020
What you can contribute
The ESP team welcomes external contributions and collaborations, including:
- Accelerator designs for a wide range of application domains
- Support for more HLS tools and libraries
See the contributing guidelines.